1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to an internal voltage generator and a method of generating an internal voltage.
2. Description of the Related Art
Generally, most semiconductor devices such as a flash memory use internal voltages internally generated for operations of the semiconductor devices in addition to an external supply voltage VDD and an external ground voltage VSS supplied from the outside.
An internal voltage having a level higher than the external supply voltage VDD or a level lower than the external ground voltage VSS may be generated by using a charge pump circuit. The charge pump circuit generates the internal voltage through a charge pumping method based on a reference voltage corresponding to a target level. The internal voltage having the level higher than the external supply voltage VDD includes a pump voltage, and the internal voltage having the level lower than the external ground voltage VSS includes a back bias voltage.
FIG. 1 is a block diagram illustrating a conventional internal voltage generator for generating a pump voltage, and FIG. 2 is a detailed diagram of a pump unit shown in FIG. 1.
Referring to FIG. 1, the internal voltage generator 10 may include a pump control unit 12 and a pump unit 14. The pump control unit 12 generates a pumping enable signal PUMP_CLK_EN based on a reference voltage VREF and a pump voltage VPUMP. The pump unit 14 generates the pump voltage VPUMP in response to the pumping enable signal PUMP_CLK_EN and a clock CLK.
The pump control unit 12 includes a comparator. The comparator may compare the reference voltage VREF with the pump voltage VPUMP and activate the pumping enable signal PUMP_CLK_EN when a level of the pump voltage VPUMP is lower than the reference voltage VREF.
The pump unit 14 generates the pump voltage VPUMP during an active duration of the pumping enable signal PUMP_CLK_EN based on the clock CLK.
Referring to FIG. 2, the pump unit 14 may include a clock sampling unit 14_1 and a charge pump 14_3. The clock sampling unit 14_1 performs a logical operation on the clock CLK and the pumping enable signal PUMP_CLK_EN to output a pumping clock PUMP_CLK. In other words, the clock sampling unit 14_1 samples the clock CLK during an active duration of the pumping enable signal PUMP_CLK_EN. The charge pump 14_3 generates the pump voltage VPUMP based on the pumping clock PUMP_CLK. The clock sampling unit 14_1 may include an AND gate, and the charge pump 14_3 may include a capacitor.
FIG. 3 is a timing diagram for explaining an operation of the conventional internal voltage generator.
Referring to FIGS. 1 to 3, the pump control unit 12 generates the pumping enable signal PUMP_CLK_EN corresponding to a voltage level of the pump voltage VPUMP. The pump control unit 12 consistently compares the reference voltage VREF with the pump voltage VPUMP and activates the pumping enable signal PUMP_CLK_EN to a logic high level when the voltage level of the pump voltage VPUMP becomes lower than the reference voltage VREF.
The pump unit 14 generates the pump voltage VPUMP based on the clock CLK and the pumping enable signal PUMP_CLK_EN. For example, the clock sampling unit 14_1 generates the pumping clock PUMP_CLK by performing an AND operation on the clock CLK and the pumping enable signal PUMP_CLK_EN. The charge pump 14_3 generates the pump voltage VPUMP based on the pumping clock PUMP_CLK.
However, in the internal voltage generator 10 having the above configuration, the charge pump 14_3 generates the pump voltage VPUMP based on the pumping clock PUMP_CLK. At this time, whenever the pumping clock PUMP_CLK shifts from a logic high level to a logic low level, the capacitor included in the charge pump 14_3 discharges charges charged therein. As the charges are discharged, the current corresponding to the charges is consumed. That is, the current consumption when the pumping clock PUMP_CLK toggles is larger than the current consumption when the pumping clock PUMP_CLK maintains a fixed logic level.
Referring back to FIG. 3, since the pumping clock PUMP_CLK toggles in the active duration of the pumping enable signal PUMP_CLK_EN, the toggling number of the pumping clock PUMP_CLK is determined depending on the active duration of the pumping enable signal PUMP_CLK_EN. The pumping clock PUMP_CLK may unnecessarily toggle (referring ‘A’) in the active duration of the pumping enable signal PUMP_CLK_EN, and the unnecessary current may be consumed by the charge pump 14_3.